Simple Circuit Description Language
Simple Circuit Description Language (SCDL) is a simple functional language to describe an arithmetic circuit over some ring. It has two basic operations, addition (+) and multiplication (). The language can be interpreted in any ring. For example, when interpreted in the Boolean field, "+" corresponds to XOR and "" corresponds to AND. I developed this language for the purpose of Fully Homomorphic Encryption (FHE). FHE allows computation to be performed on encrypted data but current schemes evaluate the computation as a circuit. Most such schemes evaluate circuits that consist of AND and XOR gates. So far an evaluator has been implemented for SCDL that can be found at https://github.com/ciphron/scdl. For documentation on the language and how to use the evaluator, see https://github.com/ciphron/scdl/blob/master/scdl.pdf.
FairplayMP Simple Function Description Language (SFDL) v2.0 Compiler to SCDL
The FairplayMP project (http://www.cs.huji.ac.il/project/Fairplay/FairplayMP.html) incorporates a compiler for a language called Simple Function Description Language (SFDL) that translates the SFDL code into a Boolean circuit. SFDL version 2.0 (http://www.cs.huji.ac.il/project/Fairplay/FairplayMP/SFDL2.0.pdf) is a simple imperative language with some constraints such as bounded loops (i.e. supporting a maximum number of iterations given by a constant) and no recursion. The circuit that is generated by the SFDLv2.0 compiler is represented by a low-level language created by the FairplayMP developers. I've written a compiler that translates that low-level language into SCDL. A vars file (see the SCDL documentation) is also automatically produced that gives a high-level description of the inputs and outputs to a program in terms of their names and types. The compiler is available at https://github.com/ciphron/sfdl_to_scdl. This compiler allows you to simply compile an SFDL file into SCDL (it first runs the SFDLv2.0 compiler in the background). Say you want to compile the included example max.sfdl, then simply run ./compile max.sdfl. Two files are produced: max.scdl and the associated vars file max.scdl.vars. Then you can use the SCDL evaluator to evaluate the circuits and the outputs are printed according to their types.