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Module Descriptor School of Computer Science and Statistics

Module CodeCS2022
Module NameComputer Architecture I
Module Short Title
ECTS
Semester Taught
Contact Hours

Lecture hours: 22, tutorial hours: 33 (11 each), Total 33.

Module PersonnelDr Michael Manzke
Learning Outcomes

Students will be able to

  • design substantial logic circuits using register transfer descriptions;
  • test and verify their design using an industry standard hardware description language (VHDL);
  • understand the organisation and execution behaviour of general-purpose processor systems;
Learning Aims

The lectures and tutorials treat the detailed design and organisation of microprocessor.

Course Work: Two projects using VHDL and ModelSim to simulate and test their design.

  1. A processor unit (ALU + shifter + fast registers) design and simulation,
  2. An instruction processor design and simulation.

Contents: Digital Logic, Register transfer definition, micro-operations, bus transfers, ALU design, shifter design, hardwired control design, microprogrammed processor control, design of an instruction processor.

The aims of the course are to learn register-transfer specification and design and learn the fundamentals of an instruction processor.

Module Content

Specific topics addressed in this module include:

  • Digital Logic
  • Register transfer language
  • ALU and shifter design
  • Multiplexer and tristate busses.
  • Datapath design
  • Instruction fetch-decode-execute cycle
Recommended Reading List

Recommended text:

  • Introductory VHDL: From Simulation to Synthesis
  • Logic and Computer Design Fundamentals” 2nd Edition updated, Mano

Additional recommended texts:

Module Prerequisites
Assessment Details

Assessment is by examination (80%) and continuous assessment (20%).

Continuous assessment is composed of a number of marked laboratory exercises and two substantial assignments.

Assessment in supplemental examinations is by 100% exam

Module Websitehttps://www.scss.tcd.ie/Michael.Manzke/index.php/mm-teaching/undergraduate/cs2022
Academic Year of Data