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Module DescriptorSchool of Computer Science and Statistics

Module CodeCS3021
Module NameComputer Architecture II
Module Short Titlen/a
Semester TaughtSemester 1
Contact HoursLecture hours:27
Lab hours:0
Tutorial hours:6

Total hours: 33
Module PersonnelDr Jeremy Jones
Learning Outcomes

Students who have successfully completed this module should be able to:

  • Write simple IA32 and x64 assembly language functions

  • Explain the IA32 and x64 procedure calling conventions

  • Write programs that mix C/C++ and IA32 or x64 assembly language functions

  • Describe the RISC design philosophy and translate simple high level language programs into RISC-I assembly language

  • Explain the key concepts behind instruction level pipelining and know how to apply a number of techniques to overcome data, load and control hazards

  • Explain the advantages of using virtual memory, show how virtual addresses are mapped to physical addresses and demonstrate how the functionality of a MMU is integrated into an operating system

  • Explain the use of a memory hierarchy to reduce effective memory access times, describe the organisation and operation of a cache, evaluate the hit rate of a cache given an address trace, develop a C/C++ cache model and know how to apply address trace analysis optimisations

  • Discuss the problems of using caches in a multiprocessor, analyse the operation of several cache coherency protocols and be able to predict the bus traffic given a sequence of CPU "memory" accesses
Learning Aims

This module focuses on the architecture of modern high performance microprocessor systems. Topics covered are basic IA32 and x64 assembly language, procedure calling conventions, the architecture of RISC CPUs, instruction level pipelining, techniques to overcome data, load and control hazards, virtual memory, caches, multiprocessors and cache coherency. This module pays particular attention to issues that improve performance and the close relationship between the hardware and the needs of the software

Module Content

Topics covered in this module are:

  • Basic IA32 and x64 assembly language

  • Procedure calling conventions (IA32 and x64)

  • Mixing C/C++ and assembly language

  • RISC vs CISC, RISC-1 design criteria and architecture, register windows and delayed jumps

  • Instruction level pipelining, DLX/MIPS pipeline, resolving data, load and control hazards

  • Virtual Memory, memory management units (MMUs), multi-level page tables, TLBs, integration of a MMU into an operating system

  • Cache organisation (L, K and N), operation, performance, address trace analysis, cache coherency

  • Multiprocessor architectures, cache coherency protocols (write-through, write-once, Firefly and MESI)
Recommended Reading List

"Computer Architecture – a Quantitative Approach", Hennessey and Patterson
"High Performance Computer Architecture", Harold Stone

Module PrerequisitesAssembly language and C/C++ programming
Assessment Details

% Exam: 80
% Coursework: 20

Tutorials and coursework account for 20% and the examination 80%.
Students must answer 3 out of 4 questions in a two hour exam.
Supplemental assessment is by 100% examination.

Module Website
Academic Year of Data2015