CS4021/4521 - Advanced Computer Architecture
Lecturer: Dr Jeremy Jones
This module focuses on locks, lockless algorithms, lockless data structures and transactional memory (see module descriptor).
|| Please hand in a short report describing what you have done (max 10 pages), Promela listing(s) and evidence that your program works (screenshots) at the 3pm lecture Wed 31-Oct-18.
| Please hand in a short report describing what you have done (max 4 pages), with source code and screenshots at SCSS reception by 4pm Fri 30-Nov-18.
|1974 A new solution of Dijkstra's concurrent programming problem, Leslie Lamport
||1993 Transactional Memory: Architectural Support for Lock-Free Data Structures, Maurice Herlihy and J. Eliot B. Moss
||2001 A pragmatic Implementation of Non Blocking Linked Lists, Timothy L Harris
||2004 Hazard Pointers: Safe Memory Reclamation for
Lock-Free Objects, Maged M. Michael
||2008 Intel® 64 Architecture Memory Ordering White Paper, Intel
||2012 Intel® Processor Identification and the CPUID Instruction, Intel Application Note 485
||2012 Intel® Architecture Instruction Set Extensions Programming Reference [chapter 8 - Intel® Transactional Synchronization Extensions]
||2013 Analysis of Haswell's Transactional Memory, David Kanter
||2013 Shared-Memory Synchronization, Michael L. Scott
2015 Intel® 64 and IA-32 Architectures Software Developer's ManualCombined Volumes: 1, 2A, 2B, 2C, 3A, 3B, 3C and 3D
||2015 Intel® 64 and IA-32 Architectures
Optimization Reference Manual [chapter 12 - Intel® TSX Recommendations]