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CS3021/3421 - Computer Architecture II

Lecturer: Dr Jeremy Jones

This module focuses on the architecture of modern high performance microprocessor systems. Topics covered are procedure calling conventions, the architecture of RISC CPUs, instruction level pipelining, virtual memory, caches, multiprocessors and cache coherency (see module descriptor).

Here is a link to last year's CS3021/3421 exam.


Introduction Introduction.pdf
IA32 and x64 IA32 + x64.pdf
t1Test.cpp, fib32.h, fib32.asm
t2Test.cpp, fib64.h, fib64.asm
RISC + pipelining RISC + pipelines.pdf
Virtual Memory MMUs.pdf
Memory Cruncher.cpp
Caches Caches.pdf
Multiprocessors and Cache Coherency Multiprocessors.pdf

Tutorials and Coursework [Marks]

Tutorial 1 t1.pdf Please hand in at the 10am lecture Mon 9-Oct-17.
Answer: t1.h, t1.asm and t1 notes.
Tutorial 2 t2.pdf Please hand in at the 10am lecture Thurs 19-Oct-17.
Answer: t2.h, t2.asm and t2 notes.
Tutorial 3 t3.pdf Please hand in at the 10am lecture Mon 13-Nov-17.
Tutorial 4 t4.pdf
Vivio Animations
Please hand in at the 3pm lecture Wed 22-Nov-16.
Answer: sample answer, t3.cpp and t3 notes.
Tutorial 5 t5.pdf This tutorial will NOT be collected and marked.
Sample solution.
Tutorial 6 t6.pdf This part of tutorial 6 will NOT be collected and marked
Tutorial 6 Coursework t6 CW.pdf
Please hand in by 16:00 Wed 20-Dec-17 at SCSS Reception ORI.
Answer: t6 2017-18.cpp

Microsoft Imagine allows you to obtain your own copy of Visual Studio and other software. Login using your TCD email address as username and the password which was automatically emailed to you when you were registered with the Microsoft DreamSpark by the School of Computer Science and Statistics.

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