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CS3021/3421 - Computer Architecture II


Lecturer: Dr Jeremy Jones

This module focuses on the architecture of modern high performance microprocessor systems. Topics covered are procedure calling conventions, the architecture of RISC CPUs, instruction level pipelining, virtual memory, caches, multiprocessors and cache coherency (see module descriptor).

Lectures

Introduction Introduction.pdf
IA32 and x64 IA32 + x64.pdf
t1Test.cpp, fib32.h, fib32.asm
t2Test.cpp, fib64.h, fib64.asm
RISC + pipelining RISC + pipelines.pdf
Virtual Memory MMUs.pdf
Memory Cruncher.cpp
Caches Caches.pdf
Multiprocessors and Cache Coherency Multiprocessors.pdf

Tutorials and Coursework

Tutorial 1 (19-Sep-18) t1.pdf Please submit your answer via Blackboard by 9am Fri 28-Sep-18.
Tutorial 2 t2.pdf Please submit your answer via Blackboard by 9am Fri 5-Oct-18.
Tutorial 3 t3.pdf Please submit your answer via Blackboard by 9am Fri 19-Oct-18.
Tutorial 4 t4.pdf
Vivio Animations
Please submit your answer via Blackboard by 9am Fri 2-Nov-18
Tutorial 5 (8-Nov-18) t5.pdf This tutorial will NOT be collected and marked (solution).
Tutorial 6 t6.pdf
matrixMultiply.cpp
helper.h
helper.cpp
makefile
Please submit your answer via Blackboard by 9am Fri 30-Nov-18.
Miscellaneous

Visual Studio is available on all SCSS Lab PCs.

Microsoft Imagine allows you to obtain your own copy of Visual Studio and other software. Login using your TCD email address as username and the password which was automatically emailed to you when you were registered with the Microsoft DreamSpark by the School of Computer Science and Statistics.

You can also use one of the SCSS Windows 10 Virtual Lab Machines (they have Visual Studio installed) through the following portal. These Virtual Lab Machines are available 24/7 and can be accessed remotely from outside College.

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