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CS3021/3421 - Computer Architecture II

Lecturer: Dr Jeremy Jones

This module focuses on the architecture of modern high performance microprocessor systems. Topics covered are procedure calling conventions, the architecture of RISC CPUs, instruction level pipelining, virtual memory, caches, multiprocessors and cache coherency (see module descriptor).


Introduction Introduction.pdf
IA32 and x64 IA32 + x64.pdf
IA32codegen.cpp, fib32.h, fib32.asm
x64codegen.cpp, fib64.h, fib64.asm
RISC + pipelining RISC + pipelines.pdf
Virtual Memory MMUs.pdf
Memory Cruncher.cpp
Caches Caches.pdf
Multiprocessors and Cache Coherency Multiprocessors.pdf

Tutorials and Coursework [Marks]

Tutorial 1 t1.pdf please hand in at the 10am lecture Thur 13-Oct-16
Tutorial 2 t2.pdf please hand in at the 3pm lecture Wed 2-Nov-16
Tutorial 3 t3.pdf please hand in at the 10am lecture Mon 14-Nov-16
Tutorial 4 t4.pdf
Vivio Animations
please hand in at the 3pm lecture Wed 23-Nov-16
Tutorial 5 t5.pdf please hand in at the 10am lecture Mon 5-Dec-16
Tutorial 6 t6.pdf please hand in by 12:00 Fri 6-Jan-17 at SCSS Reception ORI.

Microsoft Imagine allows you to obtain your own copy of Visual Studio and other software. Login using your TCD email address as username and the password which was automatically emailed to you when you were registered with the Microsoft DreamSpark by the School of Computer Science and Statistics.

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