SubmitterConfigurationVisitsDescription
dbky Q3db38 
agnewl CS3021/agnewl/q2345Configuration for CS3021 Tutorial 4, Q2. 
aitacara T4q1a44 
aitacara T4q1ALU44 
aitacara T4q1b42 
aitacara T4q1c40 
aitacara T4q1d35 
aitacara T4q1e39 
aitacara T4q1f37 
andersm3 andersm3/q1-137 
bcolwell CS3021/bcolwell/t4_148 
bcolwell CS3021/bcolwell/t4_243 
bcolwell CS3021/bcolwell/t4_347 
bcolwell CS3021/bcolwell/t4_546 
bcolwell CS3021/bcolwell/t4_643 
bcolwell CS3021/bcolwell/t4_771 
bcolwell CS3021/bcolwell/t4_7_244 
bcolwell CS3021/bcolwell/t4_848 
bcolwell CS3021/bcolwell/t4_test35 
bcolwell t4_144 
berryp <31134 will :) 
bhardwap setup2175 
bluetts TutorialQ254 
brandonm cs2630/complete115 
brandonm cs2630/complete_mutable132 
brandonm cs2630/complete_mutable_add139 
buggyr t3q2v1175 
burkely Tut v149 
burkely Tut vi156 
burkely Tut vii179 
burkely Tut4, i150 
burkely Tut4, ii143 
burkely Tut4, iii140 
burkely Tut4, iv144 
chattert CS3021/chattert/q2140 
chenx4 ALU Enable143 
cihegart q2--159program from tutorial 
ckenny5 CS3021/ckenny5/q2149Tutorial 4 Question 2 
clintonw clintonw(i)159 
clintonw Q2203 
clintonw Q3180 
clintonw T4157 
clintonw T4 - Q2162 
cmartin7 CS3021/cmartin7/Tut4/Q3/iv187Yay! :D 
cmcgarr CS3021/cmcgarr/q1.137 
concannh tut4148 
concannh tut4-3148 
corkeryg CS3021/corkeryg/q2160 
cosgroco "CS3021/cosgroco/q1.10Q1 part 1 
cronind2 CS3021/cronind2/q1230 
cronind2 CS3021/cronind2/q2192 
daboland myAnswerT4143 
daboland myT4139 
daryll multiplication92 
dbeak Q1_233 
dbeakey Q1_177 
dbeakey q1_2i43 
dbeakey Q1_341 
dbeakey Q1_437 
dbeakey Q1_532 
dbeakey Q1_630 
dbeakey Q1_840 
dowdp2 PaddyDowdTest148Testing Circuit 
durbans CS3021/durbans/q2200Tutorial 4 Q2 
durbans CS3021/durbans/q22173 
durbans durbans/q1144 
duriasm cs3021/duriasm/q2168 
duriasm test1149 
faysh question 2153questions 2 set up 
finlayp fp12143 
finlayp PF164 
flynnr3 CS3021/flynnr3/t4q1i37 
flynnr3 CS3021/flynnr3/t4q1ii35 
flynnr3 CS3021/flynnr3/t4q1iv35 
foleyj3 CS3021/foleyj3/q382 
foleyj3 CS3021/foleyj3/q2173Program for Tut4Q2 
foleyj3 CS3021/foleyj3/q3163 
gargab CS3021/gargab/q2146 
gargab cs3021/gargab/Q3144 
gargab Tutorial 4 que 1186 
gholamw gholmaw174add 
gourleys CS3021/gourleys/q2182floopedy floop 
groganco "CS3021/groganco/q20Q2 
hayesev jkhkj148 
hayesev jkhkjz139 
huntfe 1147 
huntfe 2147 
intel heh158 
jfitzpa1 q1i161test 
jinz CS3021/JIN143 
jinz CS3021/jinz/q2139 
jinz CS3021/jinz/q2new153 
jinz Zhuoyu tutorial 4138 
John yy48 
johndoe DT1173Q1 
johndoe rtrt144 
jones jones/example12295demonstrates pipeline forwarding 
jones jones/example21229branch prediction 
Juice Q3(iii)NoBranch151 
Juice Question2148Code for question two of T4 
knoxshia CS3021/knoxshia/q2153KEK 
latv CS3021/latv/q2154 
latv Tut4_Q1221 
Leon leon50 
lij9 T4Q2159 
lij9 Tutorial Q133 
lyue CS3021/lyue/q2149 
mahanley "CS3021/mahanley/q20 
mamurtag merchants162q2 
mamurtag MMM245Q2 
marco TestM113Simple test 
mcgoldc "CS3021/mcgoldc/q10 
mcgoldc CS3021/mcgoldc/q1c30 
mcgoldc Q2/p131 
mcgonaa 1.541 
mcgonaa 1.848 
mcgratc8 CS3021-t4 Question 1 c44 
mcgratc8 CS3021-t4 Question 1 d39 
mcgratc8 CS3021-t4 Question 1 e38 
mcgratc8 CS3021-t4 Question 1 f41 
mcgratc8 CS3021-t4 Question 1 V.240 
mcgratc8 CS3021/mcgratc8/q1a44 
mcgratc8 CS3021/mcgratc8/q1g51 
mcgroas mcgroaspart2144 
mckayd mckayd/q2152Question 2 Setup 
milsomj milsomj1148 
milsomj milsomj2150 
milsomj milsomjq2165 
monganai AMtut4143tutorial4 
moynihsu t4-Q253 
muganc CS3021/muganc/q1_138O1 to MUX6 
muganc CS3021/muganc/q1_240O0 to MUX7 and O1 to MUX6 (simultaneous) 
muganc CS3021/muganc/q1_334O0 to MUX8  
muganc CS3021/muganc/q1_439EX to MUX7  
muganc CS3021/muganc/q1_534Data cache to MUX9  
muganc CS3021/muganc/q1_636O0 to Zero detector 
muganc CS3021/muganc/q1_740Register File to MUX1 
muganc CS3021/muganc/q1_839Branch Target Buffer to MUX1  
murenzim Q2 of yolk141 
murenzim Q2ofyolk138 
nating NOP175Program of NOPs to quickly start from scratch when writing a new program. 
nolancr cs3021/nolancr/2152(iii) 
ocarrose CS3021/ocarrose/q2138 
oconneba 1ii129 
oconneba CS3021/oconneba/q2150 
oharaj2 T4Q2OHARAJ2137Tutorial 4 Question 2 config 
omaolaip q1-152 
omaolaip q1-241 
omaolaip q1-351 
omaolaip q1-444 
omaolaip q1-537 
omaolaip q1-649 
omaolaip q1-755 
omaolaip q1-839 
orourkge CS3021/orourkge/q1154 
orourkge CS3021/orourkge/q2156 
pappa CS3021/pappa/q2139 
phillida CS3021/phillida/q1.128 
phillida CS3021/phillida/q1.232 
phillida CS3021/phillida/q1.333 
phillida CS3021/phillida/q1.434 
phillida CS3021/phillida/q1.535 
phillida CS3021/phillida/q1.635 
phillida CS3021/phillida/q1.833 
powerm3 CS3021 Q2174Q2 
pshanaha CS3021/pshanaha/q2157Tutorial 4, Question 2 
pshanaha CS3021/pshanaha/q3145Tutorial 4, Question 3 
pshanaha CS3021/sds145 
qureshm aq/test146 
qureshm qureshm/q2162 
qureshm s151 
qureshm t142 
qureshm test153 
qureshm u142 
raesides CS3021/raesides25 
raesides sr/q1b33 
robcooney Tut4Q2151Q2 
sasharke Add&Store0 
scola Tut4 - Q2147ADD, ADD, and more ADD 
scolardf Tutorial 4 Q2145ADD 2 - Electric Boogaloo 
singlat CS3021/tushti/q2139 
sometester3 testmorestuff130<script>console.log("This should not work");</script> 
stratfob CS3021/stratfob/q2147 
tcd/Edsko Tutorial0128022Simple example program 
tcd/Edsko Tutorial027462Demonstration of basic arithmetic operations and load/store instructions 
tcd/Edsko Tutorial034276Demonstration of the branch instruction 
tcd/Edsko Tutorial041184Demonstration of the several jump and branch instructions 
tcd/Edsko Tutorial054862Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial064916Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial073740Simple program in the non-pipelined processor 
tcd/Edsko Tutorial084439Simple program in the pipelined processor 
tcd/Edsko Tutorial097121Ignoring data dependencies ("No ALU Interlock") 
tcd/Edsko Tutorial105530Stalling on data dependencies ("ALU Interlock") 
tcd/Edsko Tutorial115754Avoiding data hazards by using ALU forwarding 
tcd/Edsko Tutorial123820Ignoring load hazards ("No load interlock" and "No ALU forwarding") 
tcd/Edsko Tutorial133864Load interlocks 
tcd/Edsko Tutorial144353Load interlock combined with ALU forwarding 
tcd/Edsko Tutorial154960Demonstrating delayed branches 
tcd/Edsko Tutorial164205Demonstrating branch interlock 
tcd/Edsko Tutorial175117Demonstration of branch prediction 
tcd/Edsko Tutorial183253No zero interlock 
tcd/Edsko Tutorial193181Zero interlock 
tcd/Edsko Tutorial203305Zero forwarding 
tcd/Edsko Tutorial215678RAW Hazard 
tcd/Edsko Tutorial223053RAW Hazard (2) 
tcd/Edsko Tutorial232960RAW Hazard (for stores, 1) 
tcd/Edsko Tutorial242953RAW Hazard (for stores, 2) 
tcd/Edsko Tutorial253235RAW Hazard (for conditional branches, 1) 
tcd/Edsko Tutorial262949RAW Hazard (for conditianal branches, 2) 
tcd/Edsko Tutorial272883RAW Hazard (for indirect jumps, 1) 
tcd/Edsko Tutorial282944RAW Hazard (for indirect jumps, 2) 
tcd/Edsko Tutorial293214Load hazard 
tcd/Edsko Tutorial303166Control hazard. Notice that the first jump (which jumps to the next instruction) does not cause a jump, because the condition for the hazard (if calculated PC does not match the target PC) is not met - the calculated PC happens to be correct. 
tcd/Edsko Tutorial313258Control hazard. Note that the branch target buffer eliminates all stalls when it fills up. 
tcd/Edsko Tutorial323019Control hazard (3). Notice again that the first branch does not cause a stall because the branch is not taken (and hence, the "predicted" PC actually equals the target PC). 
teefyl q1a144 
test cs3021/test28 
test _test47A test. 
test _test239Another test. 
testing testdsfdfsfsdfs145<script>console.log("test");</script> 
theo allerparis139 
thingy thingy147 
tunstek CS3021/tunstek/q2147 
tunstek Q2 123139 
tuohydo Question2(tuohydo)44 
walshd29 CS3021/walshd29/q2182 
warrenst q1cs301235 
wetschf CS3021/WETSCH/Q1.140 
wetschf CS3021/WETSCH/Q1.237 
wetschf CS3021/WETSCH/Q1.342 
wetschf CS3021/WETSCH/Q1.441 
wetschf CS3021/WETSCH/Q1.543 
wetschf CS3021/WETSCH/Q1.638 
wetschf CS3021/WETSCH/Q1.840 
中国/edsko edsko/ctrlhaz/1231<p>Simple example of a <b>control hazard</b>. Predict the final values of registers R2 and R3. What happens when you disable Delayed Branches and instead enable Branch Interlock?</p>  
中国/edsko edsko/ctrlhaz/1b143Like edsko/ctrlhaz/1, but with an extra instruction after the delay slot. 
中国/edsko edsko/ctrlhaz/2163Control hazard: conditional branch. Predict the final value of R2. 
中国/edsko edsko/ctrlhaz/2b153Like edsko/ctrlhaz/2, but trying to take advantage of the delay slot. Note that although the SUBi instruction gets _loaded_ before the branch makes a decision, it doesn't _execute_ before the branch makes a decision and hence the effect of the SUBi won't influence the test for zero.  
中国/edsko edsko/datahaz/1185<p>Simple example of a <b>data hazard.</b></p> <ul> <li>Predict the final value of R1 before running the program.</li> <li>What changes if the enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which CPU stage is the result being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/2175<p>Another example of a <b>data hazard</b>, this time <b>involving two operand registers</b>.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which CPU stages are the results being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/2b147<p>Very minor variation on edsko/datahaz/2.</p> 
中国/edsko edsko/datahaz/3161<p>Like edsko/datahaz/2, but <b>with an unrelated instruction</b> in between the initial two ADDi and the final ADD.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which stage or stages are the results being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/4169<p>Like edsko/datahaz/2, but <b>with two unrelated instruction</b> in between the initial two ADDi and the final ADD.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? Do we need to forward any values?</li> </ul> 
中国/edsko edsko/datahaz/5163<p>Like edsko/datahaz/5, but now with <b>one of the two unrelated instructions in between the ADDis</b>.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which stages do we need to forward results, if any?</li> </ul> 
中国/edsko edsko/loadhaz/1195<p>Simple <b>load hazard</b>.</p> <ul> <li>Predict the final value of R1 before running the program.</li> <li>What happens when you enable ALU interlock? How many cycles does the program take?</li> <li>Can we solve this problem with ALU forwarding? Try it and observe what happens. From which stages are values being forwarded, if any? What is the final result?</li> <li>What happens when we enable ALU forwarding and load interlock? How many cycles does the program take? From which stages are values being forwarded, if any?</li> </ul> 
中国/edsko edsko/storehaz/1164<p>Simple example of a <b>store hazard</b>. Predict what the final value at memory address 0 will be. Experiment with store forwarding and store interlock.</p>