SubmitterConfigurationVisitsDescription
agnewl CS3021/agnewl/q2245Configuration for CS3021 Tutorial 4, Q2. 
berryp <3834 will :) 
bhardwap setup2124 
brandonm cs2630/complete68 
brandonm cs2630/complete_mutable82 
brandonm cs2630/complete_mutable_add80 
buggyr t3q2v1136 
burkely Tut v106 
burkely Tut vi106 
burkely Tut vii129 
burkely Tut4, i101 
burkely Tut4, ii99 
burkely Tut4, iii90 
burkely Tut4, iv98 
chattert CS3021/chattert/q2102 
chenx4 ALU Enable106 
cihegart q2--109program from tutorial 
ckenny5 CS3021/ckenny5/q2102Tutorial 4 Question 2 
clintonw clintonw(i)119 
clintonw Q2156 
clintonw Q3139 
clintonw T4114 
clintonw T4 - Q2115 
cmartin7 CS3021/cmartin7/Tut4/Q3/iv144Yay! :D 
concannh tut4108 
concannh tut4-3100 
corkeryg CS3021/corkeryg/q2119 
cronind2 CS3021/cronind2/q1186 
cronind2 CS3021/cronind2/q2146 
daboland myAnswerT4102 
daboland myT496 
daryll multiplication54 
dowdp2 PaddyDowdTest104Testing Circuit 
durbans CS3021/durbans/q2151Tutorial 4 Q2 
durbans CS3021/durbans/q22127 
durbans durbans/q199 
duriasm cs3021/duriasm/q2132 
duriasm test1106 
faysh question 2109questions 2 set up 
finlayp fp1299 
finlayp PF127 
foleyj3 CS3021/foleyj3/q348 
foleyj3 CS3021/foleyj3/q2132Program for Tut4Q2 
foleyj3 CS3021/foleyj3/q3121 
gargab CS3021/gargab/q2107 
gargab cs3021/gargab/Q3103 
gargab Tutorial 4 que 1141 
gholamw gholmaw130add 
gourleys CS3021/gourleys/q2138floopedy floop 
groganco "CS3021/groganco/q20Q2 
hayesev jkhkj105 
hayesev jkhkjz100 
huntfe 198 
huntfe 2104 
intel heh119 
jfitzpa1 q1i119test 
jinz CS3021/JIN101 
jinz CS3021/jinz/q2100 
jinz CS3021/jinz/q2new112 
jinz Zhuoyu tutorial 495 
John yy12 
johndoe DT1128Q1 
johndoe rtrt92 
jones jones/example12116demonstrates pipeline forwarding 
jones jones/example21181branch prediction 
Juice Q3(iii)NoBranch106 
Juice Question2103Code for question two of T4 
knoxshia CS3021/knoxshia/q2111KEK 
latv CS3021/latv/q2119 
latv Tut4_Q1184 
lij9 T4Q2112 
lyue CS3021/lyue/q2104 
mahanley "CS3021/mahanley/q20 
mamurtag merchants118q2 
mamurtag MMM204Q2 
marco TestM74Simple test 
mcgroas mcgroaspart2104 
mckayd mckayd/q2109Question 2 Setup 
milsomj milsomj1105 
milsomj milsomj2102 
milsomj milsomjq2123 
monganai AMtut495tutorial4 
murenzim Q2 of yolk95 
murenzim Q2ofyolk97 
nating NOP141Program of NOPs to quickly start from scratch when writing a new program. 
nolancr cs3021/nolancr/2107(iii) 
ocarrose CS3021/ocarrose/q299 
oconneba 1ii90 
oconneba CS3021/oconneba/q2106 
oharaj2 T4Q2OHARAJ299Tutorial 4 Question 2 config 
orourkge CS3021/orourkge/q1114 
orourkge CS3021/orourkge/q2112 
pappa CS3021/pappa/q2100 
powerm3 CS3021 Q2133Q2 
pshanaha CS3021/pshanaha/q2111Tutorial 4, Question 2 
pshanaha CS3021/pshanaha/q398Tutorial 4, Question 3 
pshanaha CS3021/sds100 
qureshm aq/test112 
qureshm qureshm/q2117 
qureshm s104 
qureshm t99 
qureshm test103 
qureshm u93 
robcooney Tut4Q2104Q2 
sasharke Add&Store0 
scola Tut4 - Q2103ADD, ADD, and more ADD 
scolardf Tutorial 4 Q2105ADD 2 - Electric Boogaloo 
singlat CS3021/tushti/q296 
sometester3 testmorestuff97<script>console.log("This should not work");</script> 
stratfob CS3021/stratfob/q2105 
tcd/Edsko Tutorial0127155Simple example program 
tcd/Edsko Tutorial027204Demonstration of basic arithmetic operations and load/store instructions 
tcd/Edsko Tutorial034083Demonstration of the branch instruction 
tcd/Edsko Tutorial041128Demonstration of the several jump and branch instructions 
tcd/Edsko Tutorial054655Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial064722Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial073579Simple program in the non-pipelined processor 
tcd/Edsko Tutorial084286Simple program in the pipelined processor 
tcd/Edsko Tutorial096964Ignoring data dependencies ("No ALU Interlock") 
tcd/Edsko Tutorial105386Stalling on data dependencies ("ALU Interlock") 
tcd/Edsko Tutorial115594Avoiding data hazards by using ALU forwarding 
tcd/Edsko Tutorial123718Ignoring load hazards ("No load interlock" and "No ALU forwarding") 
tcd/Edsko Tutorial133733Load interlocks 
tcd/Edsko Tutorial144202Load interlock combined with ALU forwarding 
tcd/Edsko Tutorial154841Demonstrating delayed branches 
tcd/Edsko Tutorial164085Demonstrating branch interlock 
tcd/Edsko Tutorial174963Demonstration of branch prediction 
tcd/Edsko Tutorial183143No zero interlock 
tcd/Edsko Tutorial193084Zero interlock 
tcd/Edsko Tutorial203186Zero forwarding 
tcd/Edsko Tutorial215533RAW Hazard 
tcd/Edsko Tutorial222939RAW Hazard (2) 
tcd/Edsko Tutorial232858RAW Hazard (for stores, 1) 
tcd/Edsko Tutorial242847RAW Hazard (for stores, 2) 
tcd/Edsko Tutorial253126RAW Hazard (for conditional branches, 1) 
tcd/Edsko Tutorial262856RAW Hazard (for conditianal branches, 2) 
tcd/Edsko Tutorial272790RAW Hazard (for indirect jumps, 1) 
tcd/Edsko Tutorial282848RAW Hazard (for indirect jumps, 2) 
tcd/Edsko Tutorial293108Load hazard 
tcd/Edsko Tutorial303052Control hazard. Notice that the first jump (which jumps to the next instruction) does not cause a jump, because the condition for the hazard (if calculated PC does not match the target PC) is not met - the calculated PC happens to be correct. 
tcd/Edsko Tutorial313166Control hazard. Note that the branch target buffer eliminates all stalls when it fills up. 
tcd/Edsko Tutorial322912Control hazard (3). Notice again that the first branch does not cause a stall because the branch is not taken (and hence, the "predicted" PC actually equals the target PC). 
teefyl q1a98 
testing testdsfdfsfsdfs102<script>console.log("test");</script> 
theo allerparis100 
thingy thingy103 
tunstek CS3021/tunstek/q2106 
tunstek Q2 12393 
walshd29 CS3021/walshd29/q2127 
中国/edsko edsko/ctrlhaz/1189<p>Simple example of a <b>control hazard</b>. Predict the final values of registers R2 and R3. What happens when you disable Delayed Branches and instead enable Branch Interlock?</p>  
中国/edsko edsko/ctrlhaz/1b102Like edsko/ctrlhaz/1, but with an extra instruction after the delay slot. 
中国/edsko edsko/ctrlhaz/2124Control hazard: conditional branch. Predict the final value of R2. 
中国/edsko edsko/ctrlhaz/2b114Like edsko/ctrlhaz/2, but trying to take advantage of the delay slot. Note that although the SUBi instruction gets _loaded_ before the branch makes a decision, it doesn't _execute_ before the branch makes a decision and hence the effect of the SUBi won't influence the test for zero.  
中国/edsko edsko/datahaz/1145<p>Simple example of a <b>data hazard.</b></p> <ul> <li>Predict the final value of R1 before running the program.</li> <li>What changes if the enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which CPU stage is the result being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/2132<p>Another example of a <b>data hazard</b>, this time <b>involving two operand registers</b>.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which CPU stages are the results being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/2b103<p>Very minor variation on edsko/datahaz/2.</p> 
中国/edsko edsko/datahaz/3122<p>Like edsko/datahaz/2, but <b>with an unrelated instruction</b> in between the initial two ADDi and the final ADD.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which stage or stages are the results being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/4124<p>Like edsko/datahaz/2, but <b>with two unrelated instruction</b> in between the initial two ADDi and the final ADD.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? Do we need to forward any values?</li> </ul> 
中国/edsko edsko/datahaz/5116<p>Like edsko/datahaz/5, but now with <b>one of the two unrelated instructions in between the ADDis</b>.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which stages do we need to forward results, if any?</li> </ul> 
中国/edsko edsko/loadhaz/1141<p>Simple <b>load hazard</b>.</p> <ul> <li>Predict the final value of R1 before running the program.</li> <li>What happens when you enable ALU interlock? How many cycles does the program take?</li> <li>Can we solve this problem with ALU forwarding? Try it and observe what happens. From which stages are values being forwarded, if any? What is the final result?</li> <li>What happens when we enable ALU forwarding and load interlock? How many cycles does the program take? From which stages are values being forwarded, if any?</li> </ul> 
中国/edsko edsko/storehaz/1122<p>Simple example of a <b>store hazard</b>. Predict what the final value at memory address 0 will be. Experiment with store forwarding and store interlock.</p>