UserConfigurationVisitsDescription
12305820 ryanc59/q1345 
12305820 ryanc59/q258 
12305820 ryanc59/q347 
12305820 ryanc59/q442 
12305820 ryanc59/q543 
12305820 ryanc59/q649 
12305820 ryanc59/q742 
12305820 ryanc59/q854 
16322635 CSU34021/mcguinmi/q1-197 
16322635 CSU34021/mcguinmi/q1-259 
16322635 CSU34021/mcguinmi/q1-358 
16322635 CSU34021/mcguinmi/q1-440 
16322635 CSU34021/mcguinmi/q1-552 
16326617 CSU34021/rmccrann/q566Data cache to MUX9 (memory data-out) 
17308703 CSU34021/pohe/q169 
17324340 CSU34021/lhackett/q145 
17324340 CSU34021/lhackett/q352 
17324340 q163 
17324340 q273 
17324340 q357 
17324340 test-154 
17324340 test-241 
17325256 blynch/Q139 
17329337 CSU34012/stkinsel/q141part 6 
17330208 t4q152 
17330567 CSU34021/hickeylu/q143 
17330567 CSU34021/hickeylu/q236 
17331147 CS34021/osullj19/q1a62 
17331147 CS34021/osullj19/q1b57 
17331147 CS34021/osullj19/q1c48 
17331147 CS34021/osullj19/q1d57 
17331147 CS34021/osullj19/q1e43 
17331147 CS34021/osullj19/q1f56 
17331147 CS34021/osullj19/q1g48 
19329891 CSU34021/boyerom/q750 
afournie CSU34021/afournie/q159 
darts q1 A37 
jharley CSU34021/jharley/q1-144 
jharley CSU34021/jharley/q1-350 
jharley CSU34021/jharley/q1-3a240 
jharley CSU34021/jharley/q1-447 
jharley CSU34021/jharley/q1-538 
jharley CSU34021/jharley/q1-645 
jharley CSU34021/jharley/q1-747 
jharley CSU34021/jharley/q1-837 
jones jones/example13062demonstrates pipeline forwarding 
jones jones/example21415branch prediction 
kirschk CSU34021/kirschk/q149 
luke CS34021/luke/q153q1 tutorial 4 
lusi sikai46 
rmccrann RMC FINAL Q212 
rmccrann CSU34021/rmccrann/q653O0 to Zero detector 
rmccrann EXam Q17 
rmccrann FINAL Q28 
rmccrann PERF X13 
rmccrann Q2 EXAM9 
rmccrann RMC14 
rmccrann RMC BRANCH15 
rmccrann RMC BRANCH PERF7 
rmccrann RMC NO NOP9 
rmccrann RRR9 
seroche CSU34021/seroche/q132 
tcd/Edsko Tutorial0131822Simple example program 
tcd/Edsko Tutorial028534Demonstration of basic arithmetic operations and load/store instructions 
tcd/Edsko Tutorial035047Demonstration of the branch instruction 
tcd/Edsko Tutorial041381Demonstration of the several jump and branch instructions 
tcd/Edsko Tutorial055886Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial065874Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial074512Simple program in the non-pipelined processor 
tcd/Edsko Tutorial085302Simple program in the pipelined processor 
tcd/Edsko Tutorial098013Ignoring data dependencies ("No ALU Interlock") 
tcd/Edsko Tutorial106232Stalling on data dependencies ("ALU Interlock") 
tcd/Edsko Tutorial116548Avoiding data hazards by using ALU forwarding 
tcd/Edsko Tutorial124376Ignoring load hazards ("No load interlock" and "No ALU forwarding") 
tcd/Edsko Tutorial134445Load interlocks 
tcd/Edsko Tutorial145150Load interlock combined with ALU forwarding 
tcd/Edsko Tutorial155615Demonstrating delayed branches 
tcd/Edsko Tutorial164808Demonstrating branch interlock 
tcd/Edsko Tutorial175770Demonstration of branch prediction 
tcd/Edsko Tutorial183802No zero interlock 
tcd/Edsko Tutorial193724Zero interlock 
tcd/Edsko Tutorial203862Zero forwarding 
tcd/Edsko Tutorial216344RAW Hazard 
tcd/Edsko Tutorial223572RAW Hazard (2) 
tcd/Edsko Tutorial233490RAW Hazard (for stores, 1) 
tcd/Edsko Tutorial243463RAW Hazard (for stores, 2) 
tcd/Edsko Tutorial253894RAW Hazard (for conditional branches, 1) 
tcd/Edsko Tutorial263480RAW Hazard (for conditianal branches, 2) 
tcd/Edsko Tutorial273414RAW Hazard (for indirect jumps, 1) 
tcd/Edsko Tutorial283472RAW Hazard (for indirect jumps, 2) 
tcd/Edsko Tutorial293761Load hazard 
tcd/Edsko Tutorial303692Control hazard. Notice that the first jump (which jumps to the next instruction) does not cause a jump, because the condition for the hazard (if calculated PC does not match the target PC) is not met - the calculated PC happens to be correct. 
tcd/Edsko Tutorial313757Control hazard. Note that the branch target buffer eliminates all stalls when it fills up. 
tcd/Edsko Tutorial323698Control hazard (3). Notice again that the first branch does not cause a stall because the branch is not taken (and hence, the "predicted" PC actually equals the target PC). 
中国/edsko edsko/ctrlhaz/1423

Simple example of a control hazard. Predict the final values of registers R2 and R3. What happens when you disable Delayed Branches and instead enable Branch Interlock?

 
中国/edsko edsko/ctrlhaz/1b323Like edsko/ctrlhaz/1, but with an extra instruction after the delay slot. 
中国/edsko edsko/ctrlhaz/2334Control hazard: conditional branch. Predict the final value of R2. 
中国/edsko edsko/ctrlhaz/2b314Like edsko/ctrlhaz/2, but trying to take advantage of the delay slot. Note that although the SUBi instruction gets _loaded_ before the branch makes a decision, it doesn't _execute_ before the branch makes a decision and hence the effect of the SUBi won't influence the test for zero.  
中国/edsko edsko/datahaz/1394

Simple example of a data hazard.

  • Predict the final value of R1 before running the program.
  • What changes if the enable ALU interlock? How many cycles does the program take?
  • What about when we enable ALU forwarding? From which CPU stage is the result being forwarded?
 
中国/edsko edsko/datahaz/2351

Another example of a data hazard, this time involving two operand registers.

  • Predict the value of R1 before running the program.
  • What happens if you enable ALU interlock? How many cycles does the program take?
  • What about when we enable ALU forwarding? From which CPU stages are the results being forwarded?
 
中国/edsko edsko/datahaz/2b317

Very minor variation on edsko/datahaz/2.

 
中国/edsko edsko/datahaz/3355

Like edsko/datahaz/2, but with an unrelated instruction in between the initial two ADDi and the final ADD.

  • Predict the value of R1 before running the program.
  • What happens if you enable ALU interlock? How many cycles does the program take?
  • What about when we enable ALU forwarding? From which stage or stages are the results being forwarded?
 
中国/edsko edsko/datahaz/4338

Like edsko/datahaz/2, but with two unrelated instruction in between the initial two ADDi and the final ADD.

  • Predict the value of R1 before running the program.
  • What happens if you enable ALU interlock? How many cycles does the program take?
  • What about when we enable ALU forwarding? Do we need to forward any values?
 
中国/edsko edsko/datahaz/5327

Like edsko/datahaz/5, but now with one of the two unrelated instructions in between the ADDis.

  • Predict the value of R1 before running the program.
  • What happens if you enable ALU interlock? How many cycles does the program take?
  • What about when we enable ALU forwarding? From which stages do we need to forward results, if any?
 
中国/edsko edsko/loadhaz/1405

Simple load hazard.

  • Predict the final value of R1 before running the program.
  • What happens when you enable ALU interlock? How many cycles does the program take?
  • Can we solve this problem with ALU forwarding? Try it and observe what happens. From which stages are values being forwarded, if any? What is the final result?
  • What happens when we enable ALU forwarding and load interlock? How many cycles does the program take? From which stages are values being forwarded, if any?
 
中国/edsko edsko/storehaz/1328

Simple example of a store hazard. Predict what the final value at memory address 0 will be. Experiment with store forwarding and store interlock.