SubmitterConfigurationVisitsDescription
dbky Q3db2 
agnewl CS3021/agnewl/q2321Configuration for CS3021 Tutorial 4, Q2. 
aitacara T4q1a12 
aitacara T4q1ALU6 
aitacara T4q1b4 
aitacara T4q1c6 
aitacara T4q1d3 
aitacara T4q1e3 
aitacara T4q1f6 
andersm3 andersm3/q1-13 
bcolwell CS3021/bcolwell/t4_119 
bcolwell CS3021/bcolwell/t4_210 
bcolwell CS3021/bcolwell/t4_313 
bcolwell CS3021/bcolwell/t4_511 
bcolwell CS3021/bcolwell/t4_614 
bcolwell CS3021/bcolwell/t4_735 
bcolwell CS3021/bcolwell/t4_7_29 
bcolwell CS3021/bcolwell/t4_812 
bcolwell CS3021/bcolwell/t4_test4 
bcolwell t4_19 
berryp <3934 will :) 
bhardwap setup2144 
bluetts TutorialQ215 
brandonm cs2630/complete89 
brandonm cs2630/complete_mutable100 
brandonm cs2630/complete_mutable_add107 
buggyr t3q2v1147 
burkely Tut v119 
burkely Tut vi130 
burkely Tut vii153 
burkely Tut4, i122 
burkely Tut4, ii114 
burkely Tut4, iii107 
burkely Tut4, iv114 
chattert CS3021/chattert/q2113 
chenx4 ALU Enable121 
cihegart q2--133program from tutorial 
ckenny5 CS3021/ckenny5/q2125Tutorial 4 Question 2 
clintonw clintonw(i)129 
clintonw Q2171 
clintonw Q3155 
clintonw T4127 
clintonw T4 - Q2131 
cmartin7 CS3021/cmartin7/Tut4/Q3/iv155Yay! :D 
cmcgarr CS3021/cmcgarr/q1.12 
concannh tut4118 
concannh tut4-3114 
corkeryg CS3021/corkeryg/q2131 
cosgroco "CS3021/cosgroco/q1.10Q1 part 1 
cronind2 CS3021/cronind2/q1200 
cronind2 CS3021/cronind2/q2161 
daboland myAnswerT4115 
daboland myT4108 
daryll multiplication66 
dbeak Q1_20 
dbeakey Q1_139 
dbeakey q1_2i14 
dbeakey Q1_35 
dbeakey Q1_44 
dbeakey Q1_55 
dbeakey Q1_62 
dbeakey Q1_86 
dowdp2 PaddyDowdTest117Testing Circuit 
durbans CS3021/durbans/q2171Tutorial 4 Q2 
durbans CS3021/durbans/q22143 
durbans durbans/q1114 
duriasm cs3021/duriasm/q2141 
duriasm test1120 
faysh question 2123questions 2 set up 
finlayp fp12111 
finlayp PF137 
flynnr3 CS3021/flynnr3/t4q1i3 
flynnr3 CS3021/flynnr3/t4q1ii2 
flynnr3 CS3021/flynnr3/t4q1iv0 
foleyj3 CS3021/foleyj3/q356 
foleyj3 CS3021/foleyj3/q2148Program for Tut4Q2 
foleyj3 CS3021/foleyj3/q3141 
gargab CS3021/gargab/q2121 
gargab cs3021/gargab/Q3117 
gargab Tutorial 4 que 1157 
gholamw gholmaw143add 
gourleys CS3021/gourleys/q2156floopedy floop 
groganco "CS3021/groganco/q20Q2 
hayesev jkhkj115 
hayesev jkhkjz111 
huntfe 1116 
huntfe 2116 
intel heh129 
jfitzpa1 q1i130test 
jinz CS3021/JIN113 
jinz CS3021/jinz/q2112 
jinz CS3021/jinz/q2new124 
jinz Zhuoyu tutorial 4106 
John yy23 
johndoe DT1143Q1 
johndoe rtrt107 
jones jones/example12133demonstrates pipeline forwarding 
jones jones/example21194branch prediction 
Juice Q3(iii)NoBranch120 
Juice Question2117Code for question two of T4 
knoxshia CS3021/knoxshia/q2122KEK 
latv CS3021/latv/q2127 
latv Tut4_Q1197 
Leon leon12 
lij9 T4Q2127 
lij9 Tutorial Q10 
lyue CS3021/lyue/q2120 
mahanley "CS3021/mahanley/q20 
mamurtag merchants133q2 
mamurtag MMM215Q2 
marco TestM86Simple test 
mcgonaa 1.56 
mcgonaa 1.813 
mcgratc8 CS3021-t4 Question 1 c10 
mcgratc8 CS3021-t4 Question 1 d8 
mcgratc8 CS3021-t4 Question 1 e9 
mcgratc8 CS3021-t4 Question 1 f9 
mcgratc8 CS3021-t4 Question 1 V.210 
mcgratc8 CS3021/mcgratc8/q1a12 
mcgratc8 CS3021/mcgratc8/q1g21 
mcgroas mcgroaspart2117 
mckayd mckayd/q2125Question 2 Setup 
milsomj milsomj1119 
milsomj milsomj2119 
milsomj milsomjq2135 
monganai AMtut4114tutorial4 
moynihsu t4-Q226 
muganc CS3021/muganc/q1_111O1 to MUX6 
muganc CS3021/muganc/q1_26O0 to MUX7 and O1 to MUX6 (simultaneous) 
muganc CS3021/muganc/q1_34O0 to MUX8  
muganc CS3021/muganc/q1_44EX to MUX7  
muganc CS3021/muganc/q1_53Data cache to MUX9  
muganc CS3021/muganc/q1_63O0 to Zero detector 
muganc CS3021/muganc/q1_76Register File to MUX1 
muganc CS3021/muganc/q1_85Branch Target Buffer to MUX1  
murenzim Q2 of yolk112 
murenzim Q2ofyolk111 
nating NOP153Program of NOPs to quickly start from scratch when writing a new program. 
nolancr cs3021/nolancr/2122(iii) 
ocarrose CS3021/ocarrose/q2111 
oconneba 1ii103 
oconneba CS3021/oconneba/q2119 
oharaj2 T4Q2OHARAJ2108Tutorial 4 Question 2 config 
omaolaip q1-117 
omaolaip q1-27 
omaolaip q1-312 
omaolaip q1-49 
omaolaip q1-57 
omaolaip q1-612 
omaolaip q1-722 
omaolaip q1-84 
orourkge CS3021/orourkge/q1128 
orourkge CS3021/orourkge/q2126 
pappa CS3021/pappa/q2110 
phillida CS3021/phillida/q1.11 
phillida CS3021/phillida/q1.21 
phillida CS3021/phillida/q1.31 
phillida CS3021/phillida/q1.41 
phillida CS3021/phillida/q1.51 
phillida CS3021/phillida/q1.62 
phillida CS3021/phillida/q1.81 
powerm3 CS3021 Q2147Q2 
pshanaha CS3021/pshanaha/q2125Tutorial 4, Question 2 
pshanaha CS3021/pshanaha/q3113Tutorial 4, Question 3 
pshanaha CS3021/sds113 
qureshm aq/test118 
qureshm qureshm/q2130 
qureshm s117 
qureshm t112 
qureshm test116 
qureshm u107 
raesides CS3021/raesides0 
raesides sr/q1b1 
robcooney Tut4Q2120Q2 
sasharke Add&Store0 
scola Tut4 - Q2115ADD, ADD, and more ADD 
scolardf Tutorial 4 Q2119ADD 2 - Electric Boogaloo 
singlat CS3021/tushti/q2111 
sometester3 testmorestuff110<script>console.log("This should not work");</script> 
stratfob CS3021/stratfob/q2118 
tcd/Edsko Tutorial0127503Simple example program 
tcd/Edsko Tutorial027294Demonstration of basic arithmetic operations and load/store instructions 
tcd/Edsko Tutorial034158Demonstration of the branch instruction 
tcd/Edsko Tutorial041153Demonstration of the several jump and branch instructions 
tcd/Edsko Tutorial054718Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial064799Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial073640Simple program in the non-pipelined processor 
tcd/Edsko Tutorial084343Simple program in the pipelined processor 
tcd/Edsko Tutorial097015Ignoring data dependencies ("No ALU Interlock") 
tcd/Edsko Tutorial105447Stalling on data dependencies ("ALU Interlock") 
tcd/Edsko Tutorial115654Avoiding data hazards by using ALU forwarding 
tcd/Edsko Tutorial123761Ignoring load hazards ("No load interlock" and "No ALU forwarding") 
tcd/Edsko Tutorial133779Load interlocks 
tcd/Edsko Tutorial144253Load interlock combined with ALU forwarding 
tcd/Edsko Tutorial154891Demonstrating delayed branches 
tcd/Edsko Tutorial164137Demonstrating branch interlock 
tcd/Edsko Tutorial175011Demonstration of branch prediction 
tcd/Edsko Tutorial183183No zero interlock 
tcd/Edsko Tutorial193124Zero interlock 
tcd/Edsko Tutorial203226Zero forwarding 
tcd/Edsko Tutorial215573RAW Hazard 
tcd/Edsko Tutorial222976RAW Hazard (2) 
tcd/Edsko Tutorial232897RAW Hazard (for stores, 1) 
tcd/Edsko Tutorial242884RAW Hazard (for stores, 2) 
tcd/Edsko Tutorial253163RAW Hazard (for conditional branches, 1) 
tcd/Edsko Tutorial262888RAW Hazard (for conditianal branches, 2) 
tcd/Edsko Tutorial272822RAW Hazard (for indirect jumps, 1) 
tcd/Edsko Tutorial282886RAW Hazard (for indirect jumps, 2) 
tcd/Edsko Tutorial293147Load hazard 
tcd/Edsko Tutorial303090Control hazard. Notice that the first jump (which jumps to the next instruction) does not cause a jump, because the condition for the hazard (if calculated PC does not match the target PC) is not met - the calculated PC happens to be correct. 
tcd/Edsko Tutorial313200Control hazard. Note that the branch target buffer eliminates all stalls when it fills up. 
tcd/Edsko Tutorial322947Control hazard (3). Notice again that the first branch does not cause a stall because the branch is not taken (and hence, the "predicted" PC actually equals the target PC). 
teefyl q1a111 
test cs3021/test7 
test _test10A test. 
test _test24Another test. 
testing testdsfdfsfsdfs116<script>console.log("test");</script> 
theo allerparis112 
thingy thingy119 
tunstek CS3021/tunstek/q2116 
tunstek Q2 123108 
tuohydo Question2(tuohydo)9 
walshd29 CS3021/walshd29/q2152 
warrenst q1cs30120 
wetschf CS3021/WETSCH/Q1.17 
wetschf CS3021/WETSCH/Q1.26 
wetschf CS3021/WETSCH/Q1.39 
wetschf CS3021/WETSCH/Q1.46 
wetschf CS3021/WETSCH/Q1.58 
wetschf CS3021/WETSCH/Q1.67 
wetschf CS3021/WETSCH/Q1.810 
中国/edsko edsko/ctrlhaz/1201<p>Simple example of a <b>control hazard</b>. Predict the final values of registers R2 and R3. What happens when you disable Delayed Branches and instead enable Branch Interlock?</p>  
中国/edsko edsko/ctrlhaz/1b117Like edsko/ctrlhaz/1, but with an extra instruction after the delay slot. 
中国/edsko edsko/ctrlhaz/2135Control hazard: conditional branch. Predict the final value of R2. 
中国/edsko edsko/ctrlhaz/2b124Like edsko/ctrlhaz/2, but trying to take advantage of the delay slot. Note that although the SUBi instruction gets _loaded_ before the branch makes a decision, it doesn't _execute_ before the branch makes a decision and hence the effect of the SUBi won't influence the test for zero.  
中国/edsko edsko/datahaz/1157<p>Simple example of a <b>data hazard.</b></p> <ul> <li>Predict the final value of R1 before running the program.</li> <li>What changes if the enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which CPU stage is the result being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/2144<p>Another example of a <b>data hazard</b>, this time <b>involving two operand registers</b>.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which CPU stages are the results being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/2b120<p>Very minor variation on edsko/datahaz/2.</p> 
中国/edsko edsko/datahaz/3130<p>Like edsko/datahaz/2, but <b>with an unrelated instruction</b> in between the initial two ADDi and the final ADD.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which stage or stages are the results being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/4138<p>Like edsko/datahaz/2, but <b>with two unrelated instruction</b> in between the initial two ADDi and the final ADD.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? Do we need to forward any values?</li> </ul> 
中国/edsko edsko/datahaz/5134<p>Like edsko/datahaz/5, but now with <b>one of the two unrelated instructions in between the ADDis</b>.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which stages do we need to forward results, if any?</li> </ul> 
中国/edsko edsko/loadhaz/1159<p>Simple <b>load hazard</b>.</p> <ul> <li>Predict the final value of R1 before running the program.</li> <li>What happens when you enable ALU interlock? How many cycles does the program take?</li> <li>Can we solve this problem with ALU forwarding? Try it and observe what happens. From which stages are values being forwarded, if any? What is the final result?</li> <li>What happens when we enable ALU forwarding and load interlock? How many cycles does the program take? From which stages are values being forwarded, if any?</li> </ul> 
中国/edsko edsko/storehaz/1133<p>Simple example of a <b>store hazard</b>. Predict what the final value at memory address 0 will be. Experiment with store forwarding and store interlock.</p>