SubmitterConfigurationVisitsDescription
dbky Q3db84 
acvillazon Problema1Mio41 
agnewl CS3021/agnewl/q2387Configuration for CS3021 Tutorial 4, Q2. 
ahmed NoPipeline29 
aitacara T4q1a71 
aitacara T4q1ALU74 
aitacara T4q1b71 
aitacara T4q1c69 
aitacara T4q1d72 
aitacara T4q1e66 
aitacara T4q1f62 
ajarteta tut33 
andersm3 andersm3/q1-171 
asdasd NO GUARDADO24111 
astaroth996 Prueba238 
astaroth996 PruebaSuma139 
astaroth996 Sum37Suma del 1 al 5, excepto el 3 
astaroth996 sumno433suma los pares hasta el 10, menos el 4 
augusto Pipetest43 
bcolwell CS3021/bcolwell/t4_175 
bcolwell CS3021/bcolwell/t4_273 
bcolwell CS3021/bcolwell/t4_377 
bcolwell CS3021/bcolwell/t4_575 
bcolwell CS3021/bcolwell/t4_671 
bcolwell CS3021/bcolwell/t4_798 
bcolwell CS3021/bcolwell/t4_7_274 
bcolwell CS3021/bcolwell/t4_880 
bcolwell CS3021/bcolwell/t4_test67 
bcolwell t4_173 
berryp <31434 will :) 
bhardwap setup2207 
Bielos FF33S39Bielos 
Bielos FF33S243Bielos 2 
bluetts TutorialQ285 
brandonm cs2630/complete158 
brandonm cs2630/complete_mutable168 
brandonm cs2630/complete_mutable_add181 
buggyr t3q2v1207 
burkely Tut v185 
burkely Tut vi190 
burkely Tut vii214 
burkely Tut4, i181 
burkely Tut4, ii179 
burkely Tut4, iii170 
burkely Tut4, iv175 
chattert CS3021/chattert/q2169 
chenx4 ALU Enable178 
cihegart q2--192program from tutorial 
ckenny5 CS3021/ckenny5/q2180Tutorial 4 Question 2 
clintonw clintonw(i)191 
clintonw Q2237 
clintonw Q3211 
clintonw T4195 
clintonw T4 - Q2193 
cmartin7 CS3021/cmartin7/Tut4/Q3/iv221Yay! :D 
cmcgarr CS3021/cmcgarr/q1.168 
concannh tut4180 
concannh tut4-3187 
corkeryg CS3021/corkeryg/q2194 
cosgroco "CS3021/cosgroco/q1.10Q1 part 1 
cronind2 CS3021/cronind2/q1265 
cronind2 CS3021/cronind2/q2227 
daboland myAnswerT4172 
daboland myT4168 
daryll multiplication127 
dbeak Q1_263 
dbeakey Q1_1107 
dbeakey q1_2i69 
dbeakey Q1_371 
dbeakey Q1_468 
dbeakey Q1_558 
dbeakey Q1_654 
dbeakey Q1_870 
dowdp2 PaddyDowdTest179Testing Circuit 
durbans CS3021/durbans/q2233Tutorial 4 Q2 
durbans CS3021/durbans/q22206 
durbans durbans/q1179 
duriasm cs3021/duriasm/q2201 
duriasm test1183 
faysh question 2188questions 2 set up 
finlayp fp12175 
finlayp PF196 
flynnr3 CS3021/flynnr3/t4q1i67 
flynnr3 CS3021/flynnr3/t4q1ii63 
flynnr3 CS3021/flynnr3/t4q1iv62 
foleyj3 CS3021/foleyj3/q3114 
foleyj3 CS3021/foleyj3/q2206Program for Tut4Q2 
foleyj3 CS3021/foleyj3/q3193 
gargab CS3021/gargab/q2178 
gargab cs3021/gargab/Q3179 
gargab Tutorial 4 que 1218 
gholamw gholmaw210add 
gourleys CS3021/gourleys/q2214floopedy floop 
groganco "CS3021/groganco/q20Q2 
hayesev jkhkj179 
hayesev jkhkjz167 
huntfe 1183 
huntfe 2191 
intel heh191 
jfitzpa1 q1i194test 
jinz CS3021/JIN175 
jinz CS3021/jinz/q2174 
jinz CS3021/jinz/q2new187 
jinz Zhuoyu tutorial 4171 
John yy81 
johndoe DT1206Q1 
johndoe rtrt177 
jones jones/example12411demonstrates pipeline forwarding 
jones jones/example21262branch prediction 
Juice Q3(iii)NoBranch186 
Juice Question2178Code for question two of T4 
knoxshia CS3021/knoxshia/q2188KEK 
latv CS3021/latv/q2187 
latv Tut4_Q1256 
Leon leon77 
lij9 T4Q2200 
lij9 Tutorial Q166 
lyue CS3021/lyue/q2186 
mahanley "CS3021/mahanley/q20 
mamurtag merchants197q2 
mamurtag MMM277Q2 
marco TestM149Simple test 
mcgoldc "CS3021/mcgoldc/q10 
mcgoldc CS3021/mcgoldc/q1c60 
mcgoldc Q2/p160 
mcgonaa 1.571 
mcgonaa 1.875 
mcgratc8 CS3021-t4 Question 1 c71 
mcgratc8 CS3021-t4 Question 1 d69 
mcgratc8 CS3021-t4 Question 1 e61 
mcgratc8 CS3021-t4 Question 1 f70 
mcgratc8 CS3021-t4 Question 1 V.271 
mcgratc8 CS3021/mcgratc8/q1a72 
mcgratc8 CS3021/mcgratc8/q1g78 
mcgroas mcgroaspart2175 
mckayd mckayd/q2189Question 2 Setup 
milsomj milsomj1180 
milsomj milsomj2182 
milsomj milsomjq2202 
monganai AMtut4175tutorial4 
moynihsu t4-Q280 
muganc CS3021/muganc/q1_164O1 to MUX6 
muganc CS3021/muganc/q1_272O0 to MUX7 and O1 to MUX6 (simultaneous) 
muganc CS3021/muganc/q1_363O0 to MUX8  
muganc CS3021/muganc/q1_471EX to MUX7  
muganc CS3021/muganc/q1_564Data cache to MUX9  
muganc CS3021/muganc/q1_666O0 to Zero detector 
muganc CS3021/muganc/q1_769Register File to MUX1 
muganc CS3021/muganc/q1_869Branch Target Buffer to MUX1  
murenzim Q2 of yolk176 
murenzim Q2ofyolk169 
nating NOP206Program of NOPs to quickly start from scratch when writing a new program. 
nolancr cs3021/nolancr/2184(iii) 
ocarrose CS3021/ocarrose/q2168 
oconneba 1ii163 
oconneba CS3021/oconneba/q2182 
oharaj2 T4Q2OHARAJ2169Tutorial 4 Question 2 config 
omaolaip q1-181 
omaolaip q1-271 
omaolaip q1-379 
omaolaip q1-474 
omaolaip q1-565 
omaolaip q1-680 
omaolaip q1-785 
omaolaip q1-866 
orourkge CS3021/orourkge/q1189 
orourkge CS3021/orourkge/q2193 
osnaiderp pc234 
pappa CS3021/pappa/q2170 
phillida CS3021/phillida/q1.159 
phillida CS3021/phillida/q1.262 
phillida CS3021/phillida/q1.362 
phillida CS3021/phillida/q1.462 
phillida CS3021/phillida/q1.562 
phillida CS3021/phillida/q1.664 
phillida CS3021/phillida/q1.860 
powerm3 CS3021 Q2209Q2 
pshanaha CS3021/pshanaha/q2190Tutorial 4, Question 2 
pshanaha CS3021/pshanaha/q3178Tutorial 4, Question 3 
pshanaha CS3021/sds176 
qureshm aq/test176 
qureshm qureshm/q2194 
qureshm s187 
qureshm t177 
qureshm test190 
qureshm u172 
raesides CS3021/raesides53 
raesides sr/q1b59 
robcooney Tut4Q2185Q2 
sasharke Add&Store0 
scola Tut4 - Q2180ADD, ADD, and more ADD 
scolardf Tutorial 4 Q2177ADD 2 - Electric Boogaloo 
singlat CS3021/tushti/q2174 
sometester3 testmorestuff161<script>console.log("This should not work");</script> 
steveni SuperExample27awkdhawiudh 
stratfob CS3021/stratfob/q2184 
tcd/Edsko Tutorial0128862Simple example program 
tcd/Edsko Tutorial027639Demonstration of basic arithmetic operations and load/store instructions 
tcd/Edsko Tutorial034412Demonstration of the branch instruction 
tcd/Edsko Tutorial041223Demonstration of the several jump and branch instructions 
tcd/Edsko Tutorial054986Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial065047Execution of a single instruction in the non-pipelined processor 
tcd/Edsko Tutorial073838Simple program in the non-pipelined processor 
tcd/Edsko Tutorial084541Simple program in the pipelined processor 
tcd/Edsko Tutorial097272Ignoring data dependencies ("No ALU Interlock") 
tcd/Edsko Tutorial105639Stalling on data dependencies ("ALU Interlock") 
tcd/Edsko Tutorial115860Avoiding data hazards by using ALU forwarding 
tcd/Edsko Tutorial123915Ignoring load hazards ("No load interlock" and "No ALU forwarding") 
tcd/Edsko Tutorial133935Load interlocks 
tcd/Edsko Tutorial144510Load interlock combined with ALU forwarding 
tcd/Edsko Tutorial155074Demonstrating delayed branches 
tcd/Edsko Tutorial164300Demonstrating branch interlock 
tcd/Edsko Tutorial175212Demonstration of branch prediction 
tcd/Edsko Tutorial183340No zero interlock 
tcd/Edsko Tutorial193252Zero interlock 
tcd/Edsko Tutorial203391Zero forwarding 
tcd/Edsko Tutorial215787RAW Hazard 
tcd/Edsko Tutorial223143RAW Hazard (2) 
tcd/Edsko Tutorial233044RAW Hazard (for stores, 1) 
tcd/Edsko Tutorial243031RAW Hazard (for stores, 2) 
tcd/Edsko Tutorial253311RAW Hazard (for conditional branches, 1) 
tcd/Edsko Tutorial263047RAW Hazard (for conditianal branches, 2) 
tcd/Edsko Tutorial272969RAW Hazard (for indirect jumps, 1) 
tcd/Edsko Tutorial283039RAW Hazard (for indirect jumps, 2) 
tcd/Edsko Tutorial293302Load hazard 
tcd/Edsko Tutorial303249Control hazard. Notice that the first jump (which jumps to the next instruction) does not cause a jump, because the condition for the hazard (if calculated PC does not match the target PC) is not met - the calculated PC happens to be correct. 
tcd/Edsko Tutorial313332Control hazard. Note that the branch target buffer eliminates all stalls when it fills up. 
tcd/Edsko Tutorial323096Control hazard (3). Notice again that the first branch does not cause a stall because the branch is not taken (and hence, the "predicted" PC actually equals the target PC). 
teefyl q1a181 
test cs3021/test55 
test _test74A test. 
test _test265Another test. 
testing testdsfdfsfsdfs178<script>console.log("test");</script> 
theo allerparis170 
thingy thingy180 
tunstek CS3021/tunstek/q2181 
tunstek Q2 123176 
tuohydo Question2(tuohydo)71 
uninorte Contreras & Acevedo0PARCIAL ESTRUCTURAS DEL COMPUTADOR II 
walshd29 CS3021/walshd29/q2212 
warrenst q1cs301263 
waye proof231 
waye proof333 
wetschf CS3021/WETSCH/Q1.172 
wetschf CS3021/WETSCH/Q1.267 
wetschf CS3021/WETSCH/Q1.371 
wetschf CS3021/WETSCH/Q1.469 
wetschf CS3021/WETSCH/Q1.573 
wetschf CS3021/WETSCH/Q1.665 
wetschf CS3021/WETSCH/Q1.869 
中国/edsko edsko/ctrlhaz/1269<p>Simple example of a <b>control hazard</b>. Predict the final values of registers R2 and R3. What happens when you disable Delayed Branches and instead enable Branch Interlock?</p>  
中国/edsko edsko/ctrlhaz/1b181Like edsko/ctrlhaz/1, but with an extra instruction after the delay slot. 
中国/edsko edsko/ctrlhaz/2196Control hazard: conditional branch. Predict the final value of R2. 
中国/edsko edsko/ctrlhaz/2b184Like edsko/ctrlhaz/2, but trying to take advantage of the delay slot. Note that although the SUBi instruction gets _loaded_ before the branch makes a decision, it doesn't _execute_ before the branch makes a decision and hence the effect of the SUBi won't influence the test for zero.  
中国/edsko edsko/datahaz/1214<p>Simple example of a <b>data hazard.</b></p> <ul> <li>Predict the final value of R1 before running the program.</li> <li>What changes if the enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which CPU stage is the result being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/2211<p>Another example of a <b>data hazard</b>, this time <b>involving two operand registers</b>.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which CPU stages are the results being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/2b177<p>Very minor variation on edsko/datahaz/2.</p> 
中国/edsko edsko/datahaz/3198<p>Like edsko/datahaz/2, but <b>with an unrelated instruction</b> in between the initial two ADDi and the final ADD.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which stage or stages are the results being forwarded?</li> </ul> 
中国/edsko edsko/datahaz/4206<p>Like edsko/datahaz/2, but <b>with two unrelated instruction</b> in between the initial two ADDi and the final ADD.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? Do we need to forward any values?</li> </ul> 
中国/edsko edsko/datahaz/5190<p>Like edsko/datahaz/5, but now with <b>one of the two unrelated instructions in between the ADDis</b>.</p> <ul> <li>Predict the value of R1 before running the program.</li> <li>What happens if you enable ALU interlock? How many cycles does the program take?</li> <li>What about when we enable ALU forwarding? From which stages do we need to forward results, if any?</li> </ul> 
中国/edsko edsko/loadhaz/1236<p>Simple <b>load hazard</b>.</p> <ul> <li>Predict the final value of R1 before running the program.</li> <li>What happens when you enable ALU interlock? How many cycles does the program take?</li> <li>Can we solve this problem with ALU forwarding? Try it and observe what happens. From which stages are values being forwarded, if any? What is the final result?</li> <li>What happens when we enable ALU forwarding and load interlock? How many cycles does the program take? From which stages are values being forwarded, if any?</li> </ul> 
中国/edsko edsko/storehaz/1198<p>Simple example of a <b>store hazard</b>. Predict what the final value at memory address 0 will be. Experiment with store forwarding and store interlock.</p>