Tutorial configurations:
namedescriptioncountlast used
Tutorial01Simple example program33,61813-Aug-22 22:12:20
Tutorial02Demonstration of basic arithmetic operations and load/store instructions9,12316-Aug-22 04:31:00
Tutorial03Demonstration of the branch instruction5,52116-Aug-22 12:44:28
Tutorial04Demonstration of the several jump and branch instructions1,53815-Aug-22 00:01:54
Tutorial05Execution of a single instruction in the non-pipelined processor6,39111-Aug-22 15:33:24
Tutorial06Execution of a single instruction in the non-pipelined processor6,22415-Aug-22 14:55:14
Tutorial07Simple program in the non-pipelined processor4,94714-Aug-22 21:10:24
Tutorial08Simple program in the pipelined processor5,93312-Aug-22 22:41:12
Tutorial09Ignoring data dependencies ("No ALU Interlock")8,38713-Aug-22 22:03:01
Tutorial10Stalling on data dependencies ("ALU Interlock")6,62415-Aug-22 17:49:18
Tutorial11Avoiding data hazards by using ALU forwarding6,98312-Aug-22 04:04:45
Tutorial12Ignoring load hazards ("No load interlock" and "No ALU forwarding")4,64114-Aug-22 23:51:43
Tutorial13Load interlocks4,70404-Aug-22 23:13:31
Tutorial14Load interlock combined with ALU forwarding5,46212-Aug-22 01:58:27
Tutorial15Demonstrating delayed branches6,03004-Aug-22 07:52:59
Tutorial16Demonstrating branch interlock5,09711-Aug-22 18:03:22
Tutorial17Demonstration of branch prediction6,08414-Aug-22 22:25:58
Tutorial18No zero interlock4,06414-Aug-22 11:16:12
Tutorial19Zero interlock3,98816-Aug-22 18:01:16
Tutorial20Zero forwarding4,16912-Aug-22 05:01:17
Tutorial21RAW Hazard6,78711-Aug-22 18:59:40
Tutorial22RAW Hazard (2)3,84010-Aug-22 05:12:49
Tutorial23RAW Hazard (for stores, 1)3,75706-Aug-22 19:20:34
Tutorial24RAW Hazard (for stores, 2)4,96216-Aug-22 17:51:39
Tutorial25RAW Hazard (for conditional branches, 1)4,13614-Aug-22 13:08:22
Tutorial26RAW Hazard (for conditianal branches, 2)3,70914-Aug-22 10:12:43
Tutorial27RAW Hazard (for indirect jumps, 1)3,64302-Aug-22 21:49:32
Tutorial28RAW Hazard (for indirect jumps, 2)3,71707-Aug-22 07:55:02
Tutorial29Load hazard4,01905-Aug-22 15:26:48
Tutorial30Control hazard. Notice that the first jump (which jumps to the next instruction) does not cause a jump, because the condition for the hazard (if calculated PC does not match the target PC) is not met - the calculated PC happens to be correct.3,95516-Aug-22 00:20:06
Tutorial31Control hazard. Note that the branch target buffer eliminates all stalls when it fills up.3,99404-Aug-22 20:10:34
Tutorial32Control hazard (3). Notice again that the first branch does not cause a stall because the branch is not taken (and hence, the "predicted" PC actually equals the target PC).3,92515-Aug-22 03:39:12
XXXXj test5031-Jul-22 17:26:08