Tutorial configurations:

name description count last used Tutorial01 Simple example program 36,447 16-Aug-26 06:47:55 Tutorial02 Demonstration of basic arithmetic operations and load/store instructions 10,237 15-Aug-26 03:23:01 Tutorial03 Demonstration of the branch instruction 6,460 15-Aug-26 03:22:46 Tutorial04 Demonstration of the several jump and branch instructions 1,983 15-Aug-26 03:22:46 Tutorial05 Execution of a single instruction in the non-pipelined processor 7,211 17-Aug-26 01:28:56 Tutorial06 Execution of a single instruction in the non-pipelined processor 6,996 16-Aug-26 22:26:36 Tutorial07 Simple program in the non-pipelined processor 5,944 17-Aug-26 16:53:04 Tutorial08 Simple program in the pipelined processor 6,919 15-Aug-26 08:36:49 Tutorial09 Ignoring data dependencies ("No ALU Interlock") 9,144 15-Aug-26 03:23:01 Tutorial10 Stalling on data dependencies ("ALU Interlock") 7,535 16-Aug-26 10:07:46 Tutorial11 Avoiding data hazards by using ALU forwarding 7,769 15-Aug-26 03:23:01 Tutorial12 Ignoring load hazards ("No load interlock" and "No ALU forwarding") 5,283 17-Aug-26 02:15:01 Tutorial13 Load interlocks 5,485 15-Aug-26 03:23:35 Tutorial14 Load interlock combined with ALU forwarding 6,370 15-Aug-26 03:22:48 Tutorial15 Demonstrating delayed branches 6,752 15-Aug-26 03:23:00 Tutorial16 Demonstrating branch interlock 5,751 15-Aug-26 03:23:01 Tutorial17 Demonstration of branch prediction 6,876 17-Aug-26 12:17:44 Tutorial18 No zero interlock 4,723 15-Aug-26 03:25:48 Tutorial19 Zero interlock 4,636 15-Aug-26 03:22:52 Tutorial20 Zero forwarding 4,870 15-Aug-26 07:52:41 Tutorial21 RAW Hazard 7,615 17-Aug-26 04:35:26 Tutorial22 RAW Hazard (2) 4,523 15-Aug-26 03:22:58 Tutorial23 RAW Hazard (for stores, 1) 4,515 15-Aug-26 03:22:52 Tutorial24 RAW Hazard (for stores, 2) 7,109 15-Aug-26 03:22:54 Tutorial25 RAW Hazard (for conditional branches, 1) 4,881 15-Aug-26 13:13:07 Tutorial26 RAW Hazard (for conditianal branches, 2) 4,450 16-Aug-26 10:20:03 Tutorial27 RAW Hazard (for indirect jumps, 1) 4,299 16-Aug-26 07:09:34 Tutorial28 RAW Hazard (for indirect jumps, 2) 4,417 15-Aug-26 03:22:46 Tutorial29 Load hazard 4,759 15-Aug-26 03:23:00 Tutorial30 Control hazard. Notice that the first jump (which jumps to the next instruction) does not cause a jump, because the condition for the hazard (if calculated PC does not match the target PC) is not met - the calculated PC happens to be correct. 4,815 16-Aug-26 16:17:49 Tutorial31 Control hazard. Note that the branch target buffer eliminates all stalls when it fills up. 4,661 15-Aug-26 03:23:00 Tutorial32 Control hazard (3). Notice again that the first branch does not cause a stall because the branch is not taken (and hence, the "predicted" PC actually equals the target PC). 4,714 15-Aug-26 03:25:45 XXXX j test 519 15-Aug-26 03:22:48