Tutorial configurations:

name description count last used Tutorial01 Simple example program 35,048 25-Apr-24 13:39:03 Tutorial02 Demonstration of basic arithmetic operations and load/store instructions 9,527 25-Apr-24 07:06:02 Tutorial03 Demonstration of the branch instruction 5,826 24-Apr-24 13:57:23 Tutorial04 Demonstration of the several jump and branch instructions 1,652 14-Apr-24 06:03:13 Tutorial05 Execution of a single instruction in the non-pipelined processor 6,627 25-Apr-24 04:40:58 Tutorial06 Execution of a single instruction in the non-pipelined processor 6,430 23-Apr-24 21:51:46 Tutorial07 Simple program in the non-pipelined processor 5,253 25-Apr-24 16:37:11 Tutorial08 Simple program in the pipelined processor 6,236 25-Apr-24 16:37:12 Tutorial09 Ignoring data dependencies ("No ALU Interlock") 8,633 24-Apr-24 04:02:57 Tutorial10 Stalling on data dependencies ("ALU Interlock") 6,838 22-Apr-24 15:07:21 Tutorial11 Avoiding data hazards by using ALU forwarding 7,225 22-Apr-24 15:07:24 Tutorial12 Ignoring load hazards ("No load interlock" and "No ALU forwarding") 4,793 25-Apr-24 13:39:30 Tutorial13 Load interlocks 4,887 25-Apr-24 23:11:37 Tutorial14 Load interlock combined with ALU forwarding 5,651 24-Apr-24 08:50:43 Tutorial15 Demonstrating delayed branches 6,235 24-Apr-24 07:55:40 Tutorial16 Demonstrating branch interlock 5,246 23-Apr-24 13:32:00 Tutorial17 Demonstration of branch prediction 6,351 22-Apr-24 15:07:39 Tutorial18 No zero interlock 4,205 22-Apr-24 15:07:43 Tutorial19 Zero interlock 4,131 22-Apr-24 15:07:48 Tutorial20 Zero forwarding 4,333 24-Apr-24 09:37:58 Tutorial21 RAW Hazard 7,012 24-Apr-24 04:01:58 Tutorial22 RAW Hazard (2) 4,013 22-Apr-24 15:07:54 Tutorial23 RAW Hazard (for stores, 1) 3,951 22-Apr-24 15:07:55 Tutorial24 RAW Hazard (for stores, 2) 6,590 22-Apr-24 15:07:57 Tutorial25 RAW Hazard (for conditional branches, 1) 4,325 22-Apr-24 15:08:01 Tutorial26 RAW Hazard (for conditianal branches, 2) 3,906 24-Apr-24 12:03:42 Tutorial27 RAW Hazard (for indirect jumps, 1) 3,788 22-Apr-24 15:08:06 Tutorial28 RAW Hazard (for indirect jumps, 2) 3,869 26-Apr-24 01:05:13 Tutorial29 Load hazard 4,223 24-Apr-24 07:29:58 Tutorial30 Control hazard. Notice that the first jump (which jumps to the next instruction) does not cause a jump, because the condition for the hazard (if calculated PC does not match the target PC) is not met - the calculated PC happens to be correct. 4,143 22-Apr-24 15:08:17 Tutorial31 Control hazard. Note that the branch target buffer eliminates all stalls when it fills up. 4,146 24-Apr-24 01:34:47 Tutorial32 Control hazard (3). Notice again that the first branch does not cause a stall because the branch is not taken (and hence, the "predicted" PC actually equals the target PC). 4,093 25-Apr-24 13:39:36 XXXX j test 216 13-Apr-24 12:24:43