This VivioJS animation is designed to help you understand the write-through cache coherency protocol.
A multiprocessor system is depicted comprising main memory, 3 CPUs and their associated caches. Main memory consists of 4 locations a0, a1, a2 and a3. The caches are direct mapped and contain two sets - addresses a0 and a2 map to set 0 and a1 and a3 to set 1.
NB: in order to simplify this animation, the size of a cache line and that of a CPU read/write operation are identical.
|Click on diagram to activate animation or here for a full screen version.|
Each CPU contains buttons which initiate read or write transactions on the specified memory location. A "CPU write" writes an incrementing value (initially 1) to "memory".
The idea is to press the buttons and see if you can follow the actions and state transitions which occur. It is possible to introduce bugs into the animation by pressing the "bug free" button in the bottom right hand corner. See if you can find out just exactly what the bugs are!
The direction of the traffic on the address and data busses are indicated by blue and red arrows respectively. The cache lines and memory location involved in the transaction are coloured green. Stale memory locations are coloured gray.
A cache line can be in one of 2 states. INVALID: cache line NOT present in cache. VALID: cache line
present in this cache and possibly other caches as well, all copies identical to copy in memory. All CPU writes are write-through.
The animation can be reset by pressing the "reset" button in the bottom right hand corner and this help information is displayed by pressing the "help" button.
Sample sequence to try [from RESET]