A multiprocessor system is depicted comprising 3 CPUs with local caches and main memory. For simplicity, main memory comprises 4 locations a0, a1, a2 and a3. The caches are direct mapped and contain two sets. The even addresses map to set 0 and the odd addresses to set 1. Each CPU contains buttons which initiate read, inc and dec transactions on the specified memory location. The CPUs also have three buttons xbegin, xend and xabort which simululate the execution of the equivalent TSX instructions. xbegin starts a transaction, xend ends the transaction and xabort aborts the transaction.
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Each cache line has a MESI state and a T bit which is set if the location is in the transaction read or write set. The 4 MESI states are INVALID: cache line NOT present in cache, EXCLUSIVE: cache line present in this cache ONLY and its value is identical to the equivalent memory location, MODIFIED: cache line present in this cache ONLY (memory copy out of date) and SHARED: cache line in this cache and possibly other caches, ALL copies identical to the equivalent memory location.
The operation of the Intel® TSX MESI cache is best described by considering a number of possible transactions.
CPU0 increments a0 using a transaction (from RESET)
CPU0 tries to increment a0 using a transaction - transaction aborted using xabort (from RESET)
CPU0 tries to increment a0 and decrement a2 using a transaction - transaction aborted due hardware limits (from RESET)
CPU0 increments a0 using a transaction - a0 initially in cache in MODIFIED state (from RESET)
CPU0 and CPU1 both try to increment a0 using a transaction - conflict detected, CPU0 transaction aborts and CPU1 transaction commits (from RESET)