This VivioJS animation is designed to help you understand the operation of the Intel® TSX MESI cache. As a detailed description of the operation of the Intel® TSX MESI cache is not readily available, this animation is a pragmatic attempt at simulating its operation (apologies in advance to Intel®). An understanding of the MESI cache coherency protocol is assumed.

A multiprocessor system is depicted comprising 3 CPUs with local caches and main memory. For simplicity, main memory comprises 4 locations a0, a1, a2 and a3. The caches are direct mapped and contain two sets. The even addresses map to set 0 and the odd addresses to set 1. Each CPU contains buttons which initiate read, inc and dec transactions on the specified memory location. The CPUs also have three buttons xbegin, xend and xabort which simululate the execution of the equivalent TSX instructions. xbegin starts a transaction, xend ends the transaction and xabort aborts the transaction.

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Each cache line has a MESI state and a T bit which is set if the location is in the transaction read or write set. The 4 MESI states are INVALID: cache line NOT present in cache, EXCLUSIVE: cache line present in this cache ONLY and its value is identical to the equivalent memory location, MODIFIED: cache line present in this cache ONLY (memory copy out of date) and SHARED: cache line in this cache and possibly other caches, ALL copies identical to the equivalent memory location.

The operation of the Intel® TSX MESI cache is best described by considering a number of possible transactions.

CPU0 increments a0 using a transaction (from RESET)

1 CPU0: xbegin CPU0 starts transaction
2 CPU0: read a0 CPU0 reads a0 from memory - state EXCLUSIVE:T
3 CPU0: inc a0 CPU0 adds one to a0 in cache ONLY - state MODIFIED:T; memory a0 NOT gray as value in cache tentative until transaction commits
4 CPU0: xend CPU0 commits transaction - a0 state MODIFIED; memory a0 gray as contents stale

CPU0 tries to increment a0 using a transaction - transaction aborted using xabort (from RESET)

1 CPU0: xbegin CPU0 starts transaction
2 CPU0: read a0 CPU0 reads a0 from memory - state EXCLUSIVE:T
3 CPU0: inc a0 CPU0 adds one to a0 in cache ONLY - state MODIFIED:T; memory a0 NOT gray as value in cache tentative until transaction commits
4 CPU0: xabort CPU0 aborts transaction and invalidates a0 - a0 state INVALID

CPU0 tries to increment a0 and decrement a2 using a transaction - transaction aborted due hardware limits (from RESET)

1 CPU0: xbegin CPU0 starts transaction
2 CPU0: read a0 CPU0 reads a0 from memory - state EXCLUSIVE:T
3 CPU0: inc a0 CPU0 adds one to a0 in cache ONLY - state MODIFIED:T; memory a0 NOT gray as value in cache tentative until transaction commits
4 CPU0: read a2 CPU0 aborts transaction as MODIFIED a0 needs to be evicted from cache to make room for a2

CPU0 increments a0 using a transaction - a0 initially in cache in MODIFIED state (from RESET)

1 CPU0: inc a0 CPU0 reads a0 from memory and adds one to a0 in cache ONLY - state MODIFIED; memory a0 gray as contents stale
2 CPU0: xbegin CPU0 starts transaction
3 CPU0: read a0 CPU0 flushes a0 to memory and then sets state to EXCLUSIVE:T
4 CPU0: inc a0 CPU0 adds one to a0 in cache ONLY - state MODIFIED:T; memory a0 NOT gray as value in cache tentative until transaction commits
5 CPU0: xend CPU0 commits transaction - a0 state MODIFIED; memory a0 gray as contents stale

CPU0 and CPU1 both try to increment a0 using a transaction - conflict detected, CPU0 transaction aborts and CPU1 transaction commits (from RESET)

1 CPU0: xbegin CPU0 starts a transaction
2 CPU1: xbegin CPU1 starts a transaction
3 CPU0: inc a0 CPU0 reads a0 from cache and adds one to a0 in cache ONLY - state MODIFIED:T; memory a0 NOT gray as value in cache tentative until transaction commits
4 CPU1: read a0 CPU1 reads a0, normally CPU0 would intervene and supply its MODIFIED cache line to CPU1, but as a0 is in CPU0's transaction writeset, it invalidates its copy of a0 and aborts its transaction; CPU 1 reads a0 from memory and sets state EXCLUSIVE:T;
5 CPU1: inc a0 CPU1 adds one to a0 in cache ONLY - state MODIFIED:T; memory a0 NOT gray as value in cache tentative until transaction commits
6 CPU1: xend CPU1 commits transaction - a0 state MODIFIED; memory a0 gray as contents stale